5. Ongoing Work

The current TSC-I2 implementation as fixed inteval PLL is not perfect yet. One of the drawbacks is that it assumes system clock to be always accurate. As we know, system clock is synchronized to NTP servers and overall it is accurate, but between synchronizations it could be affected by clock spikes and rate drift, also, the synchronization itself is subject to network jitter.

A better solution will be make the control loop a hybrid one, which integrates both PLL and FLL (Frequency Lock Loop). By doing that, offset budget due to TSC frequency drift and due to other factors could be better classified. The key point is to assign dynamic weights to PLL and FLL, so we could get both optimized rate convergence and better loop control. A fix-weighted PLL/FLL model is currently adapted by fasttime[1], a sister project of TSC-I2.

[1] Alex Holkner, fasttime, online at http://fasttime.sourceforge.net/.

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Last updated on $Date: 2005/08/29 04:28:43 $ by Xun Luo.