4. PLL Loop Controlled Clock

Data shown in this section can be downloaded here.

More testing results could be accessed here: variate the loop inteval linearly, variable the loop inteval logrithmically

PLL(Phase Lock Loop) is a mechanism to keep output signal in identical phase with input signal. If we treat system time read at each measurement as input signal, and TSC clock reading as output signal, a PLL could be designed to synchronize their phases. As we know TSC clock is of high resolution, when its accuracy is ensured, we get exactly what we want.

The current implementation of TSC-I2 adapts a fixed loop inteval PLL. The inteval is 15 seconds. Each time the loop filter is triggered, it reads current system time, TSC clock time, calculate the difference and ajust the TSC clock rate to correct future errors. It also reset the current TSC clock time to match system clock, so that offset at that moment returns to zero.

To make sure there is no sudden jumps of TSC clock time due to offset resetting, clock is only 'stepped' when the offset is above a certain threshold. When offset is under that threshold, clock is 'slewed', namely, offset compensation is amotized in several adjustments.

Below is the runnig result of PLL controled TSC clock, with offset clamped to be within 10 microseconds and rate error clamped to 0.5ppm.

Fig. 1 PLL with fixed loop: clock offset measurement during 10000 seconds(2.77hrs). Fig. 2 PLL with fixed loop: rate error measurement during 10000 seconds(2.77hrs).

Back to project homepage .
Last updated on $Date: 2005/08/29 04:28:43 $ by Xun Luo.